Computer Aided Design (CAD) for electronic systems typically involves a sequence of steps, such as layout design where devices are placed and connecting conductors are routed, layout analysis where elements representing devices and interconnect are extracted, physical verification where circuit analysis and other analyses are performed using the extracted elements, and functional verification where the design is tested against specification.
Metal fill injection is a technique that is commonly used to enhance mechanical integrity and assure planarity of the deposited layers on an integrated circuit. In multi-layer ICs, metal fill is placed in sparsely populated regions. Without the support of metal fill, layers can sag, allowing conductors of different layers to get too close. The fill typically includes many pieces, with some attached to ground and some floating unattached to ground or any other conductor. Unattached conductors or metal fill will be called floaters (or floating conductors).
The layout record for integrated circuits (ICs) normally includes the locations, shapes, and sizes of the devices and connecting metal conductors, both regular conductors and metal fill conductors. From this information, capacitors between conductors are extracted for subsequent simulation and other verification analyses.
Therefore, the purpose of metal fill is mechanical, but since it is a conductor, it can also affect the electrical operation, in particular the capacitance between connecting conductors. It is desirable to be able to determine the set of capacitors resulting from the metal fill since ignoring the effects of metal fill on capacitance could lead to inaccurate calculations and subsequently, unreliable conclusions from simulation and other analyses that verify the integrated circuit.
However, placing too much information about the metal fill in the layout record or including nodes for metal fill in subsequent simulations that use the extracted capacitors could be disadvantageous. Including fill in the layout record and in simulators encumbers the designer and the computing resources. As there can be substantial numbers of fill pieces, extraction and simulation may not be possible within normal limits on memory and CPU time.
To address these problems, methods and mechanisms for implementing virtual metal fill are provided. In some embodiments, a software-based approach (referred to herein as Virtual-Metal-Fill or VMF) that accounts for the effect of metal fill on extracted capacitance without explicitly including fill in the layout record is provided. As metal fill can be used extensively in a design, the benefit to the designer is a vastly simplified operation. Moreover, VMF software simplifies the operation by consolidating metal-fill pieces whenever the capacitance between the connecting conductors is unaffected.
In some embodiments, the metal-fill data is inserted into the layout record according to rules, with parameters and options supplied by the designer. The rules govern the electrical nature (fill is either grounded or floating) and the geometry (the size, shape, and density) of the fill. Extraction from this augmented layout record delivers various kinds of capacitors: between pieces of metal fill, between regular conductors, and between metal fill and regular conductors. Reduction schemes allow fill nodes to be eliminated, yielding an equivalent set of capacitors, just between regular conductors. Thus, virtual metal fill accounts for metal fill implicitly: the software provides detailed placement information and the final set of capacitors do not involve metal fill nodes. Designers need only provide parameters and choices for the fill rules and need not include metal fill nodes in subsequent simulations.
Therefore, the present approach can extract capacitance between conductors that accounts for metal fill without encumbering the designer to include it in the layout or in simulations. Prior approaches could overload an extraction system, making it impossible to get all the capacitors or otherwise, to use them effectively in simulations.